Design of 320/321 Prescaler Circuit Using 4/5prescaler

نویسنده

  • Chaitanya Kumar
چکیده

In this paper, Frequency divider by 2 circuit using D-flip-flop is done, based upon this a4/5 prescaler, 16/17 prescaler,32/33 prescalerareverified. Along with it the design of wide band multimodulus 320/321prescaler.CMOS single phase clock pre-scalar,wideband single phase clock 2/3 pre-scaler are also designed. A dynamic logic multiband flexible integer-N divider is designed which uses the wideband 2/3 prescaler, multimodulus,4/5 prescaler, 32/33prescaler. Frequency synthesizer is implemented by using a phase-locked loop (PLL), and it is one of the power-hungry blocks in the RF front-end modules. The firststagein a frequency synthesizeris the frequency divider which consumes a large portion of power The proposed multiband flexible dividerprovides a solution to the low power PLL synthesizers for various wireless communication devices

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design of a Low Power Multiband Clock Distribution Circuit Using Single Phase Clock

The clock distribution network consumes nearly 70% of the total power consumed by the integrated circuit since this is the only signal which has the highest switching activity. Normally for a multiband clock domain network we develop a multiple PLL to cater the need. This project aim for developing a low power true single phase clock(TSPC) multiband network which will supply for the multi clock...

متن کامل

Design of a digital PLL with divide by 4/5 prescaler employing ring oscillator TDC and accumulator type DCO

Department of Electronics and Communication Ilahia College of Engineering and Technology Muvattupuzha, Ernakulam INDIA ______________________________________________________________________________________ Abstract: A digital PLL compares the circuit frequency with a reference frequency and adjusts the output using the feedback loop. A divide by 4/5 prescaler is used. The PLL locks when both th...

متن کامل

Design and Analysis of Power and Area Efficient 2/3 Prescaler Using E-TSPC Logic

One of the important functional blocks in frequency synthesizers is the high speed dual modulus prescaler. The bottleneck of the dual modulus prescaler design is that it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) usually consists of a divide-by-2/3 prescaler unit f...

متن کامل

A 1.8V, 3GHz 16/17 Dual Modulus Prescaler in 0.35μm CMOS Technology

A dual-modulus (divide-by-16/17) prescaler has been designed using a 0.35μm CMOS technology. It consists of a divide-by-4/5 synchronous divider and a divideby-4 asynchronous divider, all implemented with MOS current mode logic. The operating frequency range is simulated to be from 0.8 to 3.1 GHz including all parasitics. The prescaler including the output buffers driving external 50Ω load draws...

متن کامل

Design and Simulation of Programmable Divider Circuit For PLL Based Frequency Synthesizer

In this paper, the divider circuit for PLL based Frequency Synthesizer has been designed. In the divider circuit, three types of counters have been used namely Prescaler, Main Counter and Swallow Counter. The Divider circuit is a two modulus Divider and it can be used to divide by any value in the range 4635 to 4650 as per the requirement. It uses a two modulus Prescaler and it has two modes of...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2015